Course Description
In this course we will begin by learning the basic code generation and register
allocation techniques for RISC machines. Next we learn about flow analysis and
apply it to develop algorithms for constructing intermediate program representations
(e.g., SSA, PDG) and implementing a suite of machine independent code optimizations
(e.g., redundancy elimination, dead code elimination). We will also study
interprocedural and array analysis techniques. Finally we will look at instruction
scheduling techniques for modern processors that support instruction level parallelism.
Syllabus
- Code Generation
- Register Allocation
- Control Flow Analysis
- Data Flow Analysis
- Program Representations
- Classical Code Optimizations
- Speculative/Profile-Guided Optimizations
- Interprocedural Analysis
- Array Dependency Analysis
- Instruction Scheduling
Reference books
- Cooper and Torczon. Engineering a Compiler. Morgan Kaufmann, 2003.
- Aho, Sethi and Ullman. Compilers: Principles, Tecniques and Tools. Addison-Wesley Publishing Company, 1995.
- Steven Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.
Course Requirements
- Assignments - 40%
- Midterm-I - 30% (March 7)
- Midterm-II - 30% (April 25)
Policies
- You are responsible for all material covered in lectures.
- You may discuss assignments with classmates, but the work you turn in must be your own. If in doubt, refer to the University's "Code of Academic Integrity" or ask the instructor. The minimum penalty for a violation of the code will be a zero for the assignment in question; the maximum penalty will be failure of the course.
- Examinations must be taken in class on the date they are given. There will be no exceptions unless you have a very good reason and have received permission in advance of the due date or examination.